Fault coverage and simplified test pattern generation for integrated circuits
US6874112B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 28, 2002 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Jun 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318307
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit with improved testability includes a test logic component that replaces a corresponding regular logic component and that generates a logic high or low whenever a test input is activated. Alternatively, it may generate either high or low depending on which of two test inputs is activated. A test program may be augmented with instructions to activate such test inputs. An integrated circuit design may be analyzed to select a node that is not covered by a test program and to identify which logic component generates an output on the node. Then the design may be altered to replace the identified logic component with a corresponding test logic component. Test coverage analysis may be based on determining whether the test program toggles the node, or determining whether a stuck at fault on the node propagates so as to be observed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.