Gain cell type non-volatile memory having charge accumulating region charged or discharged by channel current from a thin film channel path
US6876023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2002 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Jun 3, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/674
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory element subject to a threshold voltage controlling method other than those based on low leak currents or on the implantation of impurities. Such semiconductor elements are used to form semiconductor memory elements that are employed in scaled-down structures and are conducive to high-speed write operations thanks to a sufficiently prolonged refresh cycle. These semiconductor memory elements are in turn used to constitute a semiconductor memory device. A very thin semiconductor film is used as channels so that leak currents are reduced by the quantum-mechanical containment effect in the direction of film thickness. An amount of electrical charges in each charge accumulating region is used to change conductance between a source and a drain region of each read transistor structure, the conductance change being utilized for data storage. A channel of a transistor for electrically charging or discharging each charge accumulating region is made of a semiconductor film 5 nm thick at most. The arrangement affords both high-speed data write performance and an extended data retention time. The invention provides a high-speed, power-saving semiconductor device of high i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.