Electrically erasable and programmable non-volatile memory cell

US6876033B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Paolo Cappelletti · Seveso, IT
• Paolo Ghezzi · Rivolta d'Adda, IT
• Alfonso Maurelli · Vimercate, IT
• Loris Vendrame · Ponzano, IT
• Paola Zabberoni · Monza, IT

Key dates

• Filing date: Jun 25, 2003
• Grant date: Apr 5, 2005
• Expiry date: Jul 17, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/685

Abstract

An electrically erasable and programmable memory cell is provided. The memory cell includes a floating gate MOS transistor and a bipolar transistor for injecting an electric charge into the floating gate. The floating gate transistor has a source region and a drain region formed in a first well with a channel defined between the drain and source regions, a control gate region, and a floating gate extending over the channel and the control gate region. The bipolar transistor has an emitter region formed in the first well, a base region consisting of the first well, and a collector region consisting of the channel. The memory cell includes a second well that is insulated from the first well, and the control gate region is formed in the second well. Further embodiments of the present invention provide a memory including at least one such memory cell, an electronic device including such a memory, and methods of integrating a memory cell and erasing a memory cell.