Field programmable gate array
US6876228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 2003 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | May 20, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
It is one object of the present invention to provide an FPGA for which the configuration time and the time required for rewriting connection information and logic structure information can be reduced, and for which the size of the area occupied can also be reduced. In order to store connection information for an FPGA, magnetic storage elements MTJ1 to MTJn, which are memory cells of an MRAM, are provided, and using a shift register 71, connection information is written to the magnetic storage elements MTJ1 to MTJn. The shift register 71 includes register elements SR1 to SRn, which correspond to the magnetic storage elements MTJ1 to MTJn, to which the connection information is serially input and stored. When the power is switched on, the connection information stored in the magnetic storage elements MTJ1 to MTJn is latched by latch elements LT1 to LTn, and is output to switching circuits 6 to interconnect logic blocks 51.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.