Reset-pulse generator
US6876237B2 · kind B2 · utility
4Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2003 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Oct 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0231
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reset pulse generator. The CPU generates an oscillating disable signal after initialization. The oscillating circuit is coupled to the CPU to output a sequence of reset pulses to the CPU. The oscillating disable circuit is coupled to the oscillating circuit for disabling the oscillating circuit and initiating normal mode CPU operation when the oscillating disable signal is received.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.