Wide range multi-phase delay-locked loop
US6876240B2 · kind B2 · utility
20Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2003 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Dec 5, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.