Semiconductor memory device
US6876565B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2003 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Oct 17, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There are provided a plurality of first connection lines arranged in parallel with each other in a same layer, each connecting to a different contact portion; a plurality of second connection lines arranged in parallel with each other in the same layer as the first connection lines, the first connection lines and the second connection lines being arranged in an alternating fashion, and each of the second connection lines connecting to a different contact portion; a plurality of first metal wiring lines connecting to the first connection lines via first plugs; and a plurality of second metal wiring lines formed in a layer different from that of the first metal wiring lines, and connecting to the second connection lines via second plugs, the first metal wiring lines and the second metal wiring lines differing from each other with respect to at least one of thickness and width, or with respect to resistivity of wiring materials, and a product of a wiring capacitance between adjacent two of the first metal wiring lines and a wiring resistance of the first metal wiring lines being substantially the same as a product of those of the second metal wiring lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.