Differential non-volatile memory device and bit reading method for the same
US6876566B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2004 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Mar 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A differential non-volatile memory device is provided that includes setting means, at least first and second OTP memory cells that are each coupled between a supply voltage and a reference voltage, and a read circuit forming a first current path between the first memory cell and the reference voltage and a second current path between the second memory cell and the reference voltage for reading the bit and the complementary bit that are stored in the first and second memory cells. The first current path includes a first circuit point that is associated with a first output terminal, and the second current path includes a second circuit point that is associated with a second output terminal. The setting means can be activated to bring the first and second circuit points to a voltage value that is substantially equal to the reference voltage, and is able to set the value of the current flowing through each of the first and second current paths. Also provided is a method for reading such a differential non-volatile memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.