Programmable logic devices with stabilized configuration cells for reduced soft error rates
US6876572B2 · kind B2 · utility
27Cited by
5References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 21, 2003 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Jun 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Programmable logic devices are provided having configuration memory cells that exhibit decreased soft error rates. A stabilizing capacitor may be connected between each of the memory cell's input and output terminals. The capacitor may be a metal-insulator-metal capacitor formed using a vertical structure, a horizontal structure, or a hybrid vertical-horizontal structure. The memory cell may have inverter transistors of increased strength to help stabilize the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.