Timer facility for a stack or operating system
US6876601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2002 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Sep 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, comprising the steps of receiving a timeout setting, determining a selected timer unit of one of a first timer unit and a second timer unit, wherein a first set of slots is included in the first timer unit and a second set of slots is included in the second timer unit. The selected one of the timer units being determined by determining a maximum time period of the first timer unit based on a number of slots in the first set of slots and a granularity which defines a relationship between each slot in the first set of slots, comparing the timeout setting to the maximum time period of the first timer unit, and incrementing to the second timer unit if the timeout setting is greater than the maximum time period of the first timer unit. Determining one of the first slots and the second slots into which the timeout setting is to be inserted and inserting the timeout setting into the one of the slots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.