Bus interface timing adjustment device, method and application chip
US6877103B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2002 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Oct 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timing adjustment device, method and chip for a bus interface. Through repetitive adjustment of the amount of phase shift in the clocking signal to the bus interface, read/write testing of the bus interface and checking for the correctness of the read/write data, suitability of the phase shift in the memory bus clocking signal for operating normally is determined. Hence, a safety range for the amount of phase shift in the bus interface timing signal is found and the phase shift of the bus interface timing signal is set to the mid-point of the safety range. The method may also be applied to a system bus and the timing adjustment of signals between a control chipset bus and a memory bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.