Automatic generation of interconnect logic components
US6877145B2 · kind B2 · utility
4Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2001 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | May 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be ‘off-chip’. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.