Technique to assess timing delay by use of layout quality analyzer comparison
US6877147B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2002 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Jul 22, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a computer readable medium comprises at least first instructions and second instructions. The first instructions, when executed, compute a first plurality of routes. Each route of the first plurality of routes corresponds to a respective net of a plurality of nets in an integrated circuit layout, and represents a theoretically optimal route of the respective net according to a graph theory based algorithm. The second instructions, when executed, compare each of the first plurality of routes to a corresponding route of a current plurality of routes, each of the current plurality of routes corresponding to the respective net of the plurality of nets and currently existing in the integrated circuit layout. A method is also contemplated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.