Instruction architecture using two instruction stacks
US6877832B2 · kind B2 · utility
2Cited by
4References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2003 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Jul 9, 2023 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB41J2/04586
- WIPO fieldTextile and paper machines
- WIPO sectorMechanical engineering
Abstract
Systems, methods, and devices are provided for instruction architecture. One embodiment includes a first integrated circuit (IC). The first IC includes at least two instruction stacks and an arbiter coupled to the at least two instruction stacks. A second IC is provided. The first and the second ICs are coupled using a serial interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.