Panel stacking of BGA devices to form three-dimensional modules
US6878571B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2002 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Oct 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/2018
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A chip stack comprising at least one base layer including a base substrate having a first conductive pattern disposed thereon. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon which is electrically connected to the first conductive pattern of the base layer. Also included in the chip stack are at least two integrated circuit chip packages. The integrated circuit chip packages may each be electrically connected to the first conductive pattern of the base layer such that one of the integrated circuit chip packages is at least partially circumvented by the interconnect frame. Alternatively, one of the integrated circuit chip packages may be electrically connected to the first conductive pattern, with the remaining integrated circuit chip package being attached to the base substrate and at least partially circumvented by the interconnect frame such that the circumvented integrated circuit chip package and the second conductive pattern of the interconnect frame collectively define a composite footprint for the chip stack. A transposer layer may be included as a portion of each chip stack, with the transposer layer inclu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.