APS pixel with reset noise suppression and programmable binning capability
US6878918B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 9, 2003 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Jun 21, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method are described which suppresses reset noise in active pixel sensor arrays. A circuit having a number of N− wells formed in a P− silicon epitaxial layer or a number of P− wells formed in an N− silicon epitaxial layer is provided. A pixel is formed in each of the wells so that each of the wells is surrounded by silicon of the opposite polarity and an array of pixels is formed. Means are provided for selectively combining or binning adjacent N− or P− wells. During the reset period of the imaging cycle selected groups of adjacent pixels are binned and the charge injected by the resetting of a pixel is averaged among the neighboring pixels, thereby reducing the effect of this charge injection on any one of the pixels and thus reducing the noise generated. The reset is accomplished using a PMOS transistor formed in each N− well or an NMOS transistor formed in each P− well. The selective binning is accomplished using NMOS or PMOS transistors formed in the region between adjacent wells. Conductive traces between adjacent wells can also be used to accomplish the selective binning.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.