Voltage mismatch tolerant input/output buffer
US6879191B2 · kind B2 · utility
7Cited by
6References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 26, 2003 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Aug 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention include a data buffer for connecting a core of a data circuit to a data pad. External devices may couple to the data pad even if they have a different power supply voltage than does the core of the data circuit. A pass transistor is coupled between the data pad and a data node in the buffer. A control circuit monitors a signal on the data pad and drives the pass transistor according to the signal received, thereby preventing damage due to voltage mismatch between the data circuit and the external device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.