Content addressable memory (CAM) devices having error detection and correction control circuits therein and methods of operating same
US6879504B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2003 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Jul 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Content addressable memory (CAM) devices include error detection and correction (EDC) control circuits therein. The EDC control circuit operates to correct soft errors in entries within a plurality of internal CAM array blocks with, at most, limited interruption to other operations performed by the CAM device. The EDC control circuit utilizes a multi-bit check word associated with each entry to detect a soft error and perform one-bit error correction on the entry. The EDC control circuit is configured to be active during a background mode of operation when the CAM array blocks are undergoing search operations in a foreground mode of operation. A CAM array block may also include a column of dual-function check bit cells that are configured to operate as a column of CAM cells when necessary to replace a defective column of CAM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.