System and method for systolic array sorting of information segments
US6879596B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2001 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Sep 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/9047
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method have been provided for sorting information segments in a packet/cell earliest deadline first queue circuit. The invention permits information segments to be inserted at a rate that is twice as fast as the maximum extraction rate. Pairs of permanent and temporary registers are organized into a hierarchical sequence of stages. Generally, information segments with lower field ranks move systolically through the stages to temporary registers in higher sequence stages. Information segments with higher field ranks move systolically through the stages to permanent registers lower in the sequence of stages. The invention permits the highest rank information segments to be sorted and extracted with great efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.