Processor-based voice and data time slot interchange system
US6879603B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2000 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Jan 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13396
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A technique for performing a time slot interchange in a processor. The TSI process is surrounded by a multiplexing/demultiplexing circuit for converting a plurality of PCM highways into a single input serial data stream. The mux/demux circuit includes elastic stores to align frames and shift resisters to mux/demux with a minimum of delay. The TSI processor includes an input and an output buffered series port, a pair of input buffers, one to receive even-numbered frames from the PCM highways and one to receive odd-numbered frames, and an output buffer. Data is read from the appropriate input buffer in a non-sequential fashion as commanded by the processor in accordance with information stored in connection arrays (address buffers). The data is then written to the output buffer sequentially. The timing of the reading and writing steps is optimized relative to free running buffered serial port pointers for each BSP to reduce the frame delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.