Circuit and method for detecting and correcting data clocking errors
US6879650B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1999 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Jul 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0338
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a communications environment wherein data terminal equipment (DTE) transmits a data signal to data communication equipment (DCE) synchronously with a clocking signal provided by the DCE to the DTE, a circuit and method are configured to automatically detect a condition in which the data signal is sampled near a transition in the data signal, which may result in system clocking errors. Upon detecting this condition, the clocking signal used to sample the data signal is automatically inverted relative to the data signal to ensure that that the data signal is sampled near the midpoint between transitions in the data signal. In this manner, data clocking errors may be significantly reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.