Non-integer frequency divider circuit
US6879654B2 · kind B2 · utility
8Cited by
10References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 25, 2003 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Jul 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A non-integer frequency divider is disclosed. The non-integer frequency divider circuit includes several base stages connected to each other. The non-integer frequency divider circuit also includes a clocking circuit for passing an enable bit from one of the base stages to another such that only one of the base stages is enabled at any give time. The enable bit has a pulse width of one clock cycle. The outputs from the base stages are grouped together by an OR gate to generate a single output that is a fraction of an input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.