Transparent memory address remapping
US6880022B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2004 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Apr 19, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1081
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer has a hardware memory arranged into portions that are separately addressable using first identifiers, which are represented using a first number of address bits. A subsystem that is able to address a second space of the hardware memory using second identifiers initiates I/O requests directed to a device that is able to address a different, first memory space using first identifiers, which are represented using a second number of address bits. The second identifiers are initially mapped into the second memory space, but for any I/O request that meets a remapping criterion, the corresponding second identifier is remapped to one of the first identifiers that identifies a portion of the memory in the first memory space. The second space is different from the first space and the second number of address bits is greater less than the first number of address bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.