Split write data processing mechanism for memory controllers utilizing inactive periods during write data processing for other transactions
US6880057B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2000 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Jan 5, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively. By using a sideline buffer to temporarily store incomplete write instructions, processing of sequential memory access instructions can continue subject to observance of memory access conflict rules…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.