In-line code suppression
US6880074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2000 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Nov 20, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes) singly or in groups in accordance with one or more execution bits set during post-processing in opcodes preceding opcodes to be skipped. Thus portions of an application program which consume excessive power or are unsupported in particular operating environments can be easily and selectively de-activate while maintaining the integrity of the applications program. Local or cache memory is also effectively expanded and processor performance improved by eliminating opcodes from local or cache memory which will not be called.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.