Method and device for minimizing multi-layer microscopic and macroscopic alignment errors

US6881592B2 · kind B2 · utility

Assignee

• Infineon Technologies Richmond, LP · US

Inventors

• William Roberts · West Boylston, US
• Diem Thy N. Tran · Garden City, US
• Paul Jowett · Richmond, US
• Nicholas Clements · Buffalo Grove, US
• Igor Jekauc · Richmond, US
• Karen Davidson · Mechanicsville, US
• Winifried Sabisch · Munich, DE

Key dates

• Filing date: Jun 3, 2003
• Grant date: Apr 19, 2005
• Expiry date: Jun 3, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of aligning a second layer to a first layer of a semiconductor structure by forming a first layer of a wafer having a distinguished feature via a first etching process that employs a first ionized gas generating machine. Forming a second layer having a circuit pattern via a second etching process that employs a second ionized gas generating machine, wherein the forming the second layer includes minimizing relative shifting between the distinguished feature located at an edge of the wafer for the first layer and the second circuit pattern located at the edge of the wafer for the second layer.