CMOS pixel design for minimization of defect-induced leakage current
US6881992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2002 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Sep 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/803
Abstract
A pixel site of a semiconductor imager structure includes a substrate layer of a first dopant type; a photodiode being formed of a doped well region within the substrate layer, the doped well region being of a second dopant type; a transistor wherein a terminal of the transistor being provided within the doped well region, the terminal of the transistor being of the second dopant type and of a dopant concentration greater than a dopant concentration of the doped well region; and an oxide layer formed over the substrate layer, the doped well region, and the terminal of the transistor. The oxide layer has a varying height such that a height of the oxide layer associated with the doped well region is thicker than a height of the oxide layer associated with the terminal of the transistor. The oxide layer includes a step region being located where the height of the oxide layer transitions from the height associated with the doped well region to the height associated with the terminal of the transistor. The oxide layer has a constant height across a perimeter of the doped well region that forms a depletion region with the substrate when a reverse bias voltage is applied across thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.