Rectifier type frequency doubler with harmonic cancellation
US6882191B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 23, 2003 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Jun 23, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency multiplier circuit is provided that does not rely on filtering to remove unwanted harmonics and spurious content. In one implementation, a frequency doubler comprises a first rectifier doubler stage adapted to receive a first input signal having a first frequency and output a first rectified signal having multiple harmonics; a second rectifier doubler stage adapted to receive a second input signal having the first frequency and offset in phase from the first input signal and to output a second rectified signal, which has the multiple harmonics and is offset in phase from the first rectified signal; and a differential amplifier stage adapted to sum the first and second rectified signals to produce an output signal including a desired output harmonic having a frequency that is double the first frequency. The summing results in the substantial cancellation of unwanted output harmonics in the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.