Method, memory system and memory module board for avoiding local incoordination of impedance around memory chips on the memory system
US6882241B2 · kind B2 · utility
22Cited by
4References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 26, 2002 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Oct 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/0237
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A signal line of a data bus includes first wires on a first board and a second wire on a second board. The second board is installed on the first board to connect the first and second wires with each other in series to establish the signal line. Semiconductor devices are connected with the second wire. In such data bus system, impedance of the second wire is decided according to additional capacitance of the semiconductor device on the second board in order to harmonize impedance of the first board with impedance of the second board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.