Parallel counter and a multiplication logic circuit
US6883011B2 · kind B2 · utility
8Cited by
24References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2001 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Jul 4, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/607
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.