Method and apparatus for verifying hardware implementation of a processor architecture in a logically partitioned data processing system
US6883116B2 · kind B2 · utility
11Cited by
9References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 27, 2001 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Jun 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and computer instructions for testing hardware in a data processing system having multiple partitions. A monitor process in a first partition assigned to a first processor is initialized. A random code generation process in a second partition associated with a second processor is initialized. The random code generation process generates instructions and executes the instructions to test the second processor. The monitor process monitors the random code generation process and resets the second processor if the random code generation process fails.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.