Via enclosure rule check in a multi-wide object class design layout
US6883149B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2002 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Jan 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multi-wide class design layout, design rule checks for enclosure of multi wide class objects prevent false errors or false passes by performing such checks against the non-virtual boundaries of a wide class object, and not against the virtual boundaries. An exemplary embodiment provides a method for identifying as a violation, for each wide class wi object, any geometry on another layer which is located at least partially inside the wi object and has any portion thereof located within a distance encli of any non-virtual boundary of the wi object. The exemplary method is preferably performed using effective wide class objects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.