Multichip module, manufacturing method thereof, multichip unit and manufacturing method thereof
US6885099B2 · kind B2 · utility
16Cited by
5References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 22, 2003 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Oct 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15192
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Reduction of parasitic capacitance originated between semiconductor chip and optical chip by reducing the connection distance thereof by means of interlayer-connecting the semiconductor chip mounted on a surface of a resin layer and the optical chip buried on another surface of the resin layer with an interlayer via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.