Dynamic random access memory devices and method of controlling refresh operation thereof
US6885603B2 · kind B2 · utility
2Cited by
1References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2003 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Nov 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Dynamic Random Access Memory (DRAM) device can include a DRAM cell array configured to be periodically refreshed and a refresh control circuit that is configured to issue an internal refresh command to the DRAM cell array to provide periodic refresh of the DRAM cell array. The refresh control circuit can further include a refresh information signal to external of the DRAM device before the internal refresh command is issued to the DRAM cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.