Semiconductor integrated circuit device having connection pads for superposing expansion memory
US6886076B1 · kind B1 · utility
6Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2000 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Feb 3, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An IC has pads provided on the conductors that are connected to the input/output terminals of a memory block thereof so as to allow the input/output pads of an external memory chip to be connected to the pads of the IC. By superposing the memory chip on the IC with their pads mutually connected, expansion of memory is achieved without increasing the chip size. The IC has a control circuit for determining whether to use the memory block or the memory chip so as to allow switching between them as required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.