Method and apparatus for resuming memory operations from a low latency wake-up low power state
US6886105B2 · kind B2 · utility
13Cited by
21References
31Claims
0Family size
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Key dates
| Filing date | Feb 14, 2000 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Feb 14, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for resuming operations from a low latency wake-up low power state. One embodiment provides a system including a processor, an operating system, and a memory subsystem that requires initialization commands to exit a memory low power state. Control logic detects exit from an operating system low latency low power state and responsively generates a plurality of initialization commands to remove the memory subsystem from the memory low power state prior to deasserting a stop clock signal and allowing execution to resume.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.