System and method for controlling a multiplexer for selecting between an input clock and an input duty-cycle-corrected clock and outputting the selected clock and an enable signal
US6886106B2 · kind B2 · utility
4Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Oct 16, 2001 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Aug 26, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for providing a dynamically alterable output clock from an input clock based on the value of an integer, where the integer can be modified continuously. The invention also provides a sample cycle output which is an enable pulse, having the width of the input clock cycle, that is asserted one or two input clock cycles prior to the rising edge alignment of the input and output clocks, that acts as a rising edge alignment enable signal, maintaining a one-to-one correspondence between the sample cycle assertions and rising edge alignment events, regardless of the dynamic changes in the value of the integer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.