High speed methods for maintaining a summary of thread activity for multiprocessor computer systems
US6886162B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 1998 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | Jul 31, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/526
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-speed method for maintaining a summary of thread activity reduces the number of remote-memory operations for an n processor, multiple node computer system from n2 to (2n−1) operations. The method uses a hierarchical summary of-thread-activity data structure that includes structures such as first and second level bit masks. The first level bit mask is accessible to all nodes and contains a bit per node, the bit indicating whether the corresponding node contains a processor that has not yet passed through a quiescent state. The second level bit mask is local to each node and contains a bit per processor per node, the bit indicating whether the corresponding processor has not yet passed through a quiescent state. The method includes determining from a data structure on the processor's node (such as a second level bitmask) if the processor has passed through a quiescent state. If so, it is then determined from the data structure if all other processors on its node have passed through a quiescent state. If so, it is then indicated in a data structure accessible to all nodes (such as the first level bitmask) that all processors on the processor's node have passed through a quiesce…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.