Methods of incorporating germanium within CMOS process

US6887773B2 · kind B2 · utility

Assignee

• Luxtera, Inc. · US

Inventors

• Lawrence C. Gunn, III · Encinitas, US
• Giovanni Capellini · Roma, IT
• Maxime Jean Rattier · Paris, FR
• Thierry Pinguet · Cardiff-by-the-Sea, US

Key dates

• Filing date: Jun 10, 2003
• Grant date: May 3, 2005
• Expiry date: Sep 22, 2023

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/958

Abstract

Methods for deposition of a Ge layer during a CMOS process on a monolithic device are disclosed. The insertion of the Ge layer enables the conversion of light to electrical signals easily. As a result of this method, standard metals can be attached directly to the Ge in completing an electrical circuit. Vias can also be used to connect to the Ge layer. In a first aspect of the invention, a method comprises the step of incorporating the deposition of Ge at multiple temperatures in a standard CMOS process. In a second aspect of the invention, a method comprises the step of incorporating the deposition of poly-Ge growth in a standard CMOS process.