Battery backed memory with low battery voltage trip, disconnect and lockout
US6888267B2 · kind B2 · utility
5Cited by
19References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2002 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Feb 18, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system having power backup having memory circuits that may be set to a low power mode by means of volatile control registers, disconnects the memory circuits from the battery when low voltage conditions are detected so as to prevent reversion of the memory circuits to high current consumption modes such as would drain batteries after replacement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.