Electric circuit arrangement and method for checking the intactness of a photodiode array
US6888357B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2003 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Aug 1, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05B47/23
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electric circuit arrangement and method for checking intactness of both a photodiode array and an electrical connection between an array output and a microprocessor input. The array output has a high resistance when the array is inactive and intact. In case of array error, the array output is connected via in each case a defined internal resistance to ground and supply voltages. The circuit arrangement enables at any time an assessment of the status of the connection and, if the connection is intact, enables an assessment of array intactness. This is achieved by connecting the array output via a first test resistor arranged in the spatial vicinity of the array to the ground voltage and by connecting the microprocessor input via a second test resistor arranged in the spatial vicinity of the microprocessor to a microprocessor port output which can be connected either to the ground or supply voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.