Programmable interface for field programmable gate array cores
US6888371B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2002 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Jan 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable interface for FPGA cores embedded in an integrated circuit. The interface has an interconnect multiplexer (which includes demultiplexers) connected to the FPGA core and other elements of the integrated circuit. A control portion of the interface provides selection control bits to the interconnect multiplexer to make the desired connection configuration. Programmable latches in the control portion hold the selection bits which are loaded into the latches at the same time configuration bits are loaded into the integrated circuit to program the FPGA core. Alternatively, the control portion can be implemented by another FPGA core which is configured as a state machine to generate the selection control bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.