Programmable logic device with soft multiplier
US6888372B1 · kind B1 · utility
10Cited by
4References
27Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Dec 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic device is provided which includes a multi-port RAM block with a first port including first address registers and first data registers and with a second port including second address registers and a second data registers. At least one look-up table is stored in the RAM block. First programmable logic circuitry is programmed to operate as a shift register with multiple tap outputs to multiple first address registers. Second programmable logic circuitry is programmed to operate as accumulate circuitry which includes a multi-bit input coupled to multiple first data registers and includes an accumulator output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.