Digital control variable delay circuit which is hardly susceptible to noise
US6888389B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 11, 2003 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Oct 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/265
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital control variable delay circuit includes n amplitude control units which are connected in parallel and each of which receives a pair of input clock signals to be supplied to a differential pair and receives m-bit digital control signals, and a waveform shaping unit which is connected to the outputs of the n amplitude control units. Each amplitude control unit is capable of varying the amplitude of each of the pair of clock signals into (m+1) values using the m-bit digital control signals, and outputs a pair of amplitude-varied clock signals. The waveform shaping unit receives a pair of added clock signals obtained by adding and combining the pairs of amplitude-varied clock signals outputted from the n amplitude control units and outputs a pair of resultant clock signals as output signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.