High speed analog to digital converter
US6888483B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2004 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Jul 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input stage includes a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array amplifiers receives an input signal and a corresponding reference voltage at its inputs, and wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.