Content addressable memory cell
US6888730B2 · kind B2 · utility
15Cited by
13References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2002 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | May 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM) having a plurality of ternary memory cells, each ternary half cell comprising an equal number of transistors of a p-type and an n-type, the p-type transistors being formed in a first well region and the n-type transistors being formed in a second well region, the wells having at most one p+ to n+ region spacing, the transistors being interconnected to form the half ternary CAM cell and wherein the interconnections for the cell is restricted to a silicon layer and a first metal layer and connections between said cell and external signal lines is restricted to at least a second metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.