Ferroelectric memory and method of reading the same
US6888737B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 2, 2003 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Sep 2, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory includes wordlines that cross over bitlines with a ferroelectric cell at each crossing. When reading a select cell of the array, sneak currents are drawn from an active bitline. An integration amplifier begins integrating charge propagated by the active bitline, and an active wordline receives a read level voltage. A first integration value is then obtained from the integration amplifier. Following the first integration, the integration amplifier is cleared and the voltage of the active wordline reduced to a quiescent level. Integration and wordline activation are again performed to obtain a second integration value. The second value is subtracted from the first, and the difference compared to a threshold to determine a data value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.