Wireless communication device with phase-locked loop oscillator
US6888913B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 2, 2002 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Apr 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1974
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency generating circuit utilizes a quad modulus prescaler in which two control signals are used to select the prescaler modulus. The modulus control signals are generated by a multistage counter in which two independent counting stages are used to generate the first and second modulus control signals. The first modulus control signal is at a first logic level when the associated counter is at a non-zero value and is at a second logic level when the associated counter reaches zero. The second modulus control signal is generated by a second counter and has a first logic value when the second counter is in a non-zero state and a second logic value when the second counter reaches zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.