Floating point adder
US6889241B2 · kind B2 · utility
9Cited by
9References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2001 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Jan 16, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3868
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A floating point adder circuit includes an exponent path and a mantissa path. The exponent path includes a comparator to compare two three-bit exponents. The two exponents are each incremented, and a resultant exponent is chosen from one of the two original exponents or one of the incremented exponents. The mantissa path includes an adder to add mantissas, and an adder bypass path to select one of the mantissas in lieu of performing an addition. The mantissa path also includes constant shifters that conditionally shift the mantissas right by thirty-two bit positions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.