Method and apparatus for restoring registers after cancelling a multi-cycle instruction
US6889316B2 · kind B2 · utility
0Cited by
5References
24Claims
0Family size
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Key dates
| Filing date | Mar 28, 2001 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Dec 10, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a pipelined processor may be adapted to process multi-cycle instructions (MCIs). Results generated in response to non-terminal sub-instructions may be written to a speculative commit register. When the MCI commits, i.e., a terminal sub-instruction reaches the WB stage, the value in the speculative commit register may be written to the architectural register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.